One of the first questions that must be addressed in architecting the transmitter is whether the frequency synthesizer will operate on- or off-frequency relative to the PA output. On-frequency operation demands serious attention to oscillator pushing and pulling[1], and signal dynamic range can also be quite challenging particularly for WCDMA mode. Fully differential designs are almost mandatory for on-frequency architectures, particularly as die size continues to shrink and on-chip isolation is more difficult to obtain.

Oscillator re-modulation due to the PA is a particularly serious issue for on-frequency GSM-EDGE designs because a major portion of the modulation spectrum can fall within the frequency synthesizer's closed-loop bandwidth. Since the PA contributions coherently add with the oscillator's own sinusoidal waveform, the net phase error as seen by the phase-locked loop (PLL) cannot be nulled and near-chaotic behavior can result. The PLL believes that it is always behind or ahead in phase as suggested by the phasor diagram in Figure 2 and the PLL action exacerbates the problem further.

Off-frequency designs can choose between (i) a divided-down synthesizer output and (ii) an offset-mix configuration as shown in Figure 3. The voltage transfer function of the oscillator's LC resonator falls off quickly with respect to harmonics and subharmonics thereby providing immediate relief from PA-related re-modulation. Several results are tabulated versus resonator loaded-Q in Table 1.

The bandpass filter shown in Figure 3(a) and BPF2 in Figure 3(b) should be considered optional depending on other detailed design considerations. Phase noise performance of the divider in Figure 3(a) is challenging for GSM-EDGE at frequency offsets greater than 20 MHz (on the order of -165 dBc/Hz). As far as traditional digital dividers are concerned, this normally requires rail-to-rail CMOS voltage swings along with careful design, but as CMOS technology migrates into the 90 nm realm, these performance levels are more attainable. Because of noise considerations, dividers must use a minimum number of active devices in circuit structures like differential cascade voltage switch logic (DCVSL)[5].

CMOS frequency dividers are ideally memoryless from one RF cycle to the next because they operate rail-to-rail. In contrast, a high-Q LC oscillator extracts only a small portion of the total stored reactive energy each cycle, and this is an important factor in achieving low-noise performance. Greater insight into the underlying differences is captured in Razavi's expanded definition of resonator Q based on phase-slope rather than energy storage[3]. These concepts make injection-locked dividers worthy of consideration, particularly for older process nodes where phase noise performance margins are slim.

The frequency-offset method shown in Figure 3(b) avoids most of the divider noise issues associated with Figure 3(a) in exchange for noise and linearity issues associated with the offset mixer. A single-sideband mixer is normally used to reduce the requirements for BPF1, which is present to reduce the unwanted sideband and LO feed-through from the mixer.

Few requirements for 3G transceivers are easy to achieve, but some requirements are certainly more difficult to achieve than others. The GSM-EDGE specification poses severe spectral requirements at 400 kHz and 20 MHz frequency offsets. Receive band noise is also a demanding requirement. Output spurious-tone performance often separates first-silicon from production-level silicon; spurs are always a serious challenge.

For WCDMA, dynamic range and error vector magnitude (EVM) are frequently the pacing transmitter requirements that must be contended with. Modulation accuracy is increasingly difficult as more advanced signals like HSDPA and HSUPA come on the scene.

When it comes to design challenges, power consumption and die area cannot be left out of the discussion. Too frequently, these important product attributes are not accurately known until well into a design cycle where it is difficult to make mid-course corrections. Mid-course corrections are rarely localized to one or two small blocks in the design.

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