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The basic concept of auto power down for dynamic power management (APD-DPM) is to shut down devices automatically when no events occur and wake them up when an event is sensed at the input of the event-driven design (EDD) block. Specifically, an EDD block will turn on only when there is a change in the input signal. If there is no change on the input, then power to the EDD block remains off and retains the virtual output value to the next stage.

If the EDD block is turned off in between operations, a malfunction can result. APD-DPM is designed in such a way that after power down, the output stage maintains the output value. Figures 1 and 2 show the conceptual block diagram of APD-DPM along with the waveform.

The next section describes the implementation of APD-DPM logic. APD-DPM logic consists of an event sensor, power on/off logic, on period logic, input buffer, and output stage. The function of “event sensor” is to continuously monitor the input signal and generate a short pulse at each transaction (such as high to low or low to high). Every rising edge of the pulse signal that comes out of the event-sensor block is an indication to “power on/off” logic to turn on the power line. The “on period” logic decides when to turn off the power line through the “power on/off” logic. Depending on the signal received from the two blocks (event sensor and on period logic) “power on/off” logic turns the power line on or off as appropriate. During the power off, the output-stage retains the output value (until the input change) for the next stage.

Multipliers are one of the most important elements in digital filters such as finite impulse response (FIR) and infinite impulse response (IIR) filters. These filters are used in a wide variety of digital signal-processing (DSP) applications. The 4-bit multiplier used is an array multiplier. The multiplicand is multiplied by each bit of the multiplier starting from the least significant bit. Each such multiplication forms a partial product. Successive partial products are shifted one position to the left. The final product is obtained from the sum of the partial products.

Consider the following binary multiplication of a two 4-bit integer value. To implement this, 4-bit full adders (adder), 4-bit SISO (top), 4-bit PIPO (bottom) registers, and 2-bit counter (CNT) are used, as shown in Figure 3, without APD logic.

Figure 4 shows a block diagram of a 4-bit multiplier with APD-DPM logic. Simulation results are tabulated in Table 1. With the APD technique, the 4-bit multiplier block's power consumption is 55%; a power reduction of 45%.

Likewise, the EDD, as shown in Figure 1, is implemented using dual-edge-triggered D flip-flops (DET-DFFs). We have monitored/measured current flowing through the EDD block and manually calculated power (power = voltage to EDD * current flowing through EDD). Voltage to EDD is 2.5 V and current is shown in Table 1 for a 4-bit multiplier. Figure 5 offers a comparison between power consumed by the EDD using DET-DFF circuit with APD and without APD.

Simulated results show that with the APD-DPM technique, power consumption for a 4-bit multiplier (EDD) is 55%; a power reduction of 45%. Similarly, for a DET-DFF circuit with APD-DPM, power consumption is 30%; a power reduction of 70%.

1. Sinha A. Chandrakasan A, “Dynamic Power Management in Wireless Sensor Network,” Design & Test of Computers, IEEE vol. 18, issue 2, March/April 2001, pp. 62-74.

Girish N. Jadhav is a senior member of the Analog Engineering Department at Ikanos Communications Inc. in Fremont, Calif, where he is responsible for PLL design and silicon characterization of analog transmitters and receivers. He received his B.E. degree in Electronics & Telecommunication from the University of Karnataka, India in 1999.