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Although, CMOS technology itself can't compete with GaAs, HBT, SiGe or BiCMOS technologies, a CMOS Tx can be integrated with a powerful DSP. Thus, by using DSP many CMOS deficiencies can be alleviated. For example, by using a predistortion technique for a PA along with the DSP, the nonlinearity problem can be dramatically improved. For an efficiency-related problem, the techniques such as polar loop, Doherty, dynamic bias or linear amplification with nonlinear components (LINC) can improve the performance. The major building blocks in a highly integrated Tx are a PA, a modulator (MOD), a power detector (PD), an automatic gain control circuit (AGC) and the voltage-controlled oscillator (VCO). Typical implementation of each of these blocks will be discussed.

The CMOS PA has gradually replaced the HBT or GaAs FET in the low to medium (up to 20 dBm) power applications like Bluetooth and WLAN at 2.4 GHz to 2.5 GHz and 5.1 GHz to 5.9 GHz. For a CMOS IC, the common-mode noise is an issue. The differential configuration is the answer. The output power can be combined at the final stage with a balun or left it as a differential interface if the post PA SAW is balanced or a dipole type antenna is used.

A PA design's emphasis is on the output power, power gain, linearity and efficiency. The design starts at the output port where the output power contours of the device are characterized. Once the output termination is determined, the matching circuit is designed the same way as the other RF building block's matching circuits. A two-stage common-source FET with the RC feedback is shown in Figure 1(a). M1 and M2 are the driver stages. M3 and M4 are the output power stages. RC feedback from the drain to the gate stabilizes the transistors at the high frequency. The feedback also widens the bandwidth of the PA. M5 and M6 and M7 and M8 are the active resistive dividers to bias the driver stage and the power stage, respectively. The cascode PA design is popular as well. One such implementation is shown in Figure 1(b). Topology wise, it is similar to a cascode LNA. The advantage of the cascode configuration is to reduce the Miller multiply effect. Miller effect comes into play because of the parasitic capacitance between a FET's gate and its drain. In a common-source (CS) amplifier, it will be a problem. By inserting a common gate (CG) stage in the cascode configuration, the output and input are isolated. The input capacitance is also reduced. The additional advantage is more gain for the same amount of bias current since the bias current is reused. M1 through M4 are the driver stage while M5 to M8 complete the power stage. An integrated balun is used in this design since most widely used antennas in wireless devices are single ended.

A PD is used to monitor the PA's output power level. The PD's output dc voltage is fed back to the baseband for processing. A PD can be implemented in many ways. It could be as simple as a diode or a FET circuit. Or it could be as complicated as a circuit with hundreds of transistors. The level of complexity depends on the requirements for a PD. The important design parameters for a PD are dynamic range, linear-in-dB linearity, power consumption, ease of integration and its operating frequency.

A PD with one simple FET is presented in Figure 2. The basic idea is to use the square term of the active device. M1 is the active device. M1 is biased at the borderline between triode and saturation region. It means the Vbias or Vgs is set to be Vds + Vt. The drain of the FET is close to zero. So if Vgs is slightly higher than Vt will bias M1 at the border line between the triode and saturation region. The standard equation for the drain current of a FET transistor in the saturation region is as follow:

K is the device parameter that includes the physical dimensions of the device, electron mobility and oxide capacitance. Since Vgs = Vds + Vt, then Vds can be expressed as Vds = Vgs-Vt. Equation 1 can be further simplified to:

With equation 2, the square law relationship between the input RF signal and output-rectified current is established. This is why the RF input is applied at the drain, not M1's gate. The rectified output current goes through load resistor R3 to establish the output voltage. R2 and C3 are the output filter. A FET can be configured in a common-source configuration as in an amplifier. It has the square law characteristics as seen in equation 1. But the Vt term will create an undesired dc offset term.

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