An integrated power management solution must be designed to meet the needs of the applications processor and peripherals it supports (Figure 2). In particular, it must correctly sequence the individual power supplies. Voltage domains requiring the highest supplies must be activated first in order to prevent IC latch up. It must provide constant power to supplies that must be “always on” to provide for functions such as persistent data storage and sleep capabilities. It also needs to monitor the battery to ensure the voltage supplied remains in range.

There are a couple of key specifications to consider. First, consider the quiescent current of each regulator. While this number may be small, consider its impact when it is magnified 10 or 20 times by other regulators and functions in the device.

Also, consider the power supply rejection ratio (PSRR), which measures the level of disturbance in the power supply after regulation. If the level of disturbance is high, it can result in unpleasant tones in the audio band and add modulation on the RF signals, which can interfere with transmissions and require expensive filtering.

To achieve high PSRR across a wide frequency band, the LDO error amplifier usually has its bias current set for the highest output current, which is the worst case operating condition. As this bias is fixed, and independent of current demand, this results in the amplifier being overbiased and consuming a higher quiescent current than required at low current demands. For this reason, a high-performance LDO design usually needs to have a low-power sleep mode to reduce the inefficiency at low current demands.

A unique approach to the problem uses a patented design technique known as the Smart Mirror LDO regulator, a part with higher PSRR performance compared to other regulators (Figure 3).

The Smart Mirror regulators mirror the output current demand back to the bias generator, which allows the bias to be reduced automatically as demand falls and gives dynamic quiescent current control. This gives a regulator with high PSRR and dynamic performance over a range of operating currents, without being constrained by the usual design compromise of being overbiased under all conditions except when under maximum load. Having an autonomous adaptive bias control also removes the need for a low-power operating mode and hence any user intervention to switch to a lower-power mode at low current demands.

Supplying 10 mA, an LDO using this technique offers typically 99% current efficiency, consuming less than 20 microamperes. In addition, power supply rejection is maintained at higher levels over higher bandwidths — at 217 Hz, a Smart Mirror regulator offers more than 80 dB PSRR; at 10 kHz, the PSRR is still above 60 dB.

In addition to multiple high-performance LDOs, other components of a highly integrated power management IC (PMIC) would typically include high-efficiency buck converters with programmable output voltages, individually selectable LED drivers, programmable battery charger, audio drivers, and possibly other functions.

Buck converters improve the efficiency of the circuit and reduce thermal power dissipation. A dc-dc buck converter with integrated switches can provide a high current, low-voltage supply to the baseband circuit, with synchronous and asynchronous modes ensuring efficiency across a range of current demands. Power efficiencies of more than 90% can be achieved compared to approximately 50% for an LDO in typical applications. This extends the talk and standby time of mobile handsets.

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