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Wireless systems of all types — commercial, military and space — have evolved in recent years to increased system complexity at ever more stringent power budgets^[1]. To meet market requirements, years of research and development have gone into the application of silicon CMOS technologies to complex RF functions to leverage the core values of low power and integration^[2]. Relying on advanced CMOS process technologies, system architectures are now based on digital schemes that can often be provided in a single baseband chip for a complex and often multistandard solution. RF sections have not yet found a single semiconductor technology that can serve a similar role, so multichip module (MCM) solutions have been the preferred approach. Also, CMOS performance in RF markets has previously been limited to frequency ranges of a few GHz.

In this article, we present the first pure CMOS RFIC operating in Ku band, thereby pushing product-level performance available from UltraCMOS technology to a substantially higher level. With this product development, engineers can begin to see a path to highly integrated RFIC solutions from dc to 14 GHz.

UltraCMOS technology is a fully depleted CMOS technology made in a 100 nm thick Si film on sapphire. Advantages of forming UltraCMOS CMOS transistors on a pure sapphire substrate are manifold including the following:

• low capacitance, hence high speed at low power;

• fully depleted operation, improving linearity, speed and low-voltage performance;

• excellent RF performance:

• f_max typically 3x f_t (60 GHz at L = 0.5 µm; and 100 GHz at 0.25 µm);

• very high linearity (+38 dBm IP3 mixers);

• high Q integrated passives (Q_L > 40 at 2 GHz for 5 nH inductor);

• high isolation (>80 dB between adjacent devices);

• integrated EEPROM available without additional masks or process steps

• multiple threshold options without additional cost;

• an extremely low-loss substrate at RF frequencies;

• inherent radiation hardness;

• up to 2 kV HBM ESD protection with low parasitics; and

• processed in standard CMOS facilities on large wafers.

Figure 1 shows a cross-section of the UltraCMOS technology. Above the sapphire substrate is a conventional CMOS process; and the sapphire provides unmatched RF substrate performance.

Ku band is heavily used for satellite communications of all types. Point to point, broadcast (TV, etc.) and VSAT applications have been made possible by this 10 GHz to 14 GHz band. Traditionally, all the RF components have been made in III-V semiconductor technologies, especially gallium arsenide (GaAs). For several reasons, a typical radio architecture sets the radio noise figure (NF) with a very low noise amplifier (often a GaAs PHEMT device) followed by a mixer to downconvert to lower frequencies where signal conditioning is both cheaper and performed at lower power.

To allow flexible reuse of systems, it is desirable to use a programmable phase-locked loop (PLL) chip for local oscillator (LO) generation for the downconversion mixer. Low-cost single-chip PLLs running in Ku band are not available, especially one qualified for a space or military environment. Such PLLs are available, however, at up to 3.5 GHz and are widely used as a low cost and high-performance alternative to expensive discrete PLL modules^[1]. Therefore, a 4:1 prescaler can be used to divide 14 GHz LO output signals down to 3.5 GHz, at which point these PLL chips can maintain phase and frequency lock for the system.

Figure 2 shows the block diagram of the PE9308 UltraCMOS 4:1 prescaler. It was designed to cover C band through Ku band (6 GHz to 14 GHz) and to provide an output signal that could be fed directly to standard PLL control chips. Existing products such as PE9304 offers 4:1 prescaler functions up through 6 GHz, so addition of the PE9308 provides a frequency synthesis solution from essentially dc through 14 GHz in two CMOS chips.

Achieving such high-frequency operation required use of Peregrine Semiconductor's new 0.25 µm UltraCMOS technology. Previous products using the more established 0.5 µm technology were limited to operation at or below about 6 GHz, depending on the class of product. Other than scaling the gate length, however, the rest of the process remains the same, especially the high-performance passive devices, which has the benefit of enabling the same level of integration in 0.25 µm as in 0.5 µm.

Figure 3 shows the input sensitivity curve measured for the new prescaler chip. As can be seen, the device shows excellent sensitivity throughout its design band (the 6 GHz to 7 GHz range is not shown). Power consumption for the part is 17 mA at 2.5 V (Vdd) for a total power consumption of about 50 mW compared to previously popular Ku prescalers made in GaAs, which consume about 500 mW. Also, the device operates from a single positive supply voltage.

Since many systems at these high frequencies are assembled as chip-on-board using alumina substrates, the PE9308 is available in packaged and chip form. Careful simulation of the parasitics must be included in the layout. This is especially true for CMOS devices because their input is a gate capacitor. Therefore, matching to a capacitor requires the correct amount of inductance to provide a real 50 Ω match. This creates a potential for resonance that can be useful, as seen in Figure 3. At about 8.3 GHz, the input circuit is at resonance, thereby increasing the voltage at the prescaler's CMOS input. Here, the property of CMOS transistors comes into play since they are pure transconductance devices that take input voltage and create an output current. So, the increased input voltage provides 10 dB to 20 dB sensitivity improvement near the resonance peak. This effect can be used for narrowband systems by adjusting the input matching elements. Multiple bond wires can be used to adjust the inductance as shown in Figure 4, but it is important to model accurately the mutual inductance in multiwire bonds.

The divide-by-four output power is shown in Figure 5, meeting or exceeding the design spec of 0 dBm over the entire band of operation. The PLL chips that receive this signal have a minimum sensitivity of -5 dBm, so the output power from the prescalers has sufficient margin to provide a two-chip solution for frequency synthesis up through Ku band.

The Ku prescaler described above is the first product to be released in the 0.25 µm UltraCMOS process. But the potential for integration remains the same as in the proven 0.5 µm process. Figure 6 shows an example of a highly integrated RF system (dual-band, high anti-jam GPS chip for military applications), while Figure 7 reveals an integrated subsystem, an IF downconverter with digital gain control for space applications. As shown, the key benefit of a sapphire substrate is very high levels of RF integration, specifically the ability to include a high percentage of passive devices.

This dual-band, high A/J GPS receiver chip includes virtually all active and passive components with the exception of the PLL loop filters elements (due to their large values); four SAW filters; and about a dozen decoupling capacitors. Channel isolation is provided by tuned RF amplifiers rather than a diplexer to save area. An all-digital loop sets the gain of each channel using two digital step attenuators: a single 20 dB step and a six bit with 1 dB steps (~30 dB range).

Since both channels must operate simultaneously, high isolation between the two synthesizer loops, especially on spurious noise, is required. To achieve this, one PLL is an integer-N device and the other a fractional-N device. This ensures that the spurious tones are never the same between the two channels. In addition, about 5k gates of digital signal processing are included to implement a quarter-rate conversion and digital filtering.

Combining these features into a single chip enabled substantial system-level advantages over the previous solution. Specifically, area reduction of more than 90%; power reduction of more than 60% and component number reduction of more than 90% were achieved.

Likewise, Figure 7 shows the block diagram of an IF downconverter that has also been reduced to a single UltraCMOS chip.

In Figure 8, we show the current MCM requiring multiple variable gain amplifiers (VGA) and chip and wire assembly of multiple components. Use of digital attenuators was more complex with many components, hence the choice of VGAs with their known power consumption and design issues.

Figure 9 shows a single chip solution to the entire line-up of Figure. 7. Key to its usefulness is integration of two 32 dB (six bit) digital step attenuators (DSA), both of which are controlled through a single serial interface. Use of digital attenuators has two key advantages:

1. The entire gain control loop remains digital, simplifying design and test; and

2. Gain blocks can be designed as fixed gain rather than variable gain, improving stability and power consumption.

DSAs require high value and high precision resistors integrated with low loss and low distortion switches. The control function and serial interface takes fewer than one thousand logic gates, which is trivial for CMOS technology to integrate and consume less than 100 µA of current. The fixed gain blocks reduce power consumption because their range of required operation is reduced as compared to a variable gain amplifier. Since the part is designed in the UltraCMOS process it meets all radiation hardness requirements of the satellite application.

A new module based on the IC of Figure 9 reduces part count by approximately 65%. This is especially valuable in long-term space programs, or constellations, where obsolete parts can cause expensive and time-consuming redesign or re-qualification. Area, weight and assembly costs fall proportionately with part count reduction. And the simpler design of fixed gain amplifiers offers broader bandwidth and higher performance than VGAs, which extends the chip's usefulness in multiple frequency line-ups.

We have shown that MCM solutions become smaller, less expensive, and less complex with the substitution of highly integrated IC solutions as building blocks inside the MCMs. Area and part count savings of 65% to 90% have been demonstrated. These benefits apply in diverse applications from high-volume, low-cost commercial mobile handsets to low-volume, high-reliability satellite payloads. RFIC integration complements, rather than competes with MCM approaches in RF systems.

1. For example, see www.psemi.com for space PLL products.

2. R. Reedy & M.C. Comparini, “Perspective of RF CMOS/Mixed Signal Integration in Next-Generation Satellite Systems,” EuMW 2003.

3. Dan Nobbe, “Integration-by-parts: An Approach to the RFIC Market,” RF Design, pp. 26-30, February 2004.

Ronald Reedy is Peregrine Semiconductor Corp.'s co-founder and serves as chief technical officer and vice president for sales, space and defense. Previously, Reedy led the microelectronics division at Navy Research and Development (NRaD) and was engaged in fiber communications and photonic systems R&D. He is a co-inventor of UTSi technology and has more than 20 years experience in semiconductor R&D. He received his B.S. from the U.S. Naval Academy and his Ph.D. from University of California at San Diego, Calif.

Mark Burgener is one of three co-founders of Peregrine Semiconductor. He is currently vice president of Advanced Products. His group is active in the development of future products and is responsible for the timely and smooth transition from development to production. He holds a doctoral degree in physics and is principal and co-author of numerous patents and papers. In the early years of Peregrine, Burgener was instrumental in the development of the UltraCMOS technology.

Fleming Lam is a senior engineer of Peregrine Semiconductor's Advanced Products. He is currently active in the development of future products for Peregrine Semiconductor. Lam received his B.S. from the University of California at Davis and has seven years of experience in integrated circuit design including high-speed prescalers, synthesizers, RF switches, automatic gain control, and other RF circuits.

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