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Automated circuit extraction dramatically speeds complex interconnect modeling Sep 1, 2007 12:00 PM By Michael Heimlich Traditional RF/microwave design approaches no longer meet the challenges of next-generation communication products. An alternative methodology has been developed. Besides describing the new automated circuit extraction (ACE) technology, this article discusses real-world design examples to demonstrate its accuracy and efficiency.
Real-world examples
Example 1 — MMIC distributed amplifier design:
A monolithic microwave integrated circuit (MMIC) distributed amplifier depends on the interstage interconnects to define its impedance and bandwidth characteristics. Figure 1 shows such a design using pseudomorphic high electron mobility transistor (PHEMT) technology initialed modeling the interconnects with distributed MLIN, MBEND, MTEE, etc,. models but, for example, no coupling among adjacent arms of the meandered interstage lines. Using ACE software with a large coupling radius specified yields greater bandwidth, but at the expense of gain flatness; the culprit is the couplings, shown in extracted schematic form in Figure 2. By reducing the ACE coupling radius, it can be seen that the majority of the detrimental coupling is due to the adjacent arms of the meandered interconnects (Figure 3). In a matter of minutes, the ACE technology empowers the designer to identify, pinpoint, and redesign the circuit, whereas iterating with layout and EM analysis would likely take the better part of a day or days. Example 2 — A module/printed circuit board (PCB) design problem:
In this example, ACE capabilities are applied to a complex, 16-layer PCB application (Figure 4) early in the design flow in order to efficiently and accurately design the RF transmit signal path, shown here with the copper-colored power and ground planes as complete fills. The large transceiver chip requires a good deal of bypassing that adds more than a few nets to the control lines and RF signal path. All in all, at this stage of the design, the 16-layer board has approximately 75 nets, dozens of vias, and 160 ports. Analyzing this large a design with a 3-D planar solver is a time-consuming task because of the time required to create the Green's function for the multiple, non-uniform layers. Three-D FEM techniques would also take a long time — even longer because of the amount of metal. Even 3-D finite-difference time-domain (FDTD) software products would suffer due to the high port count. Using ACE with this design provides an answer in a little more than one second when modeling all the coupled lines with the GMCLIN MOM models. |
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