For the PDF version of this article, click here.

Modern radio systems, like those based on UWB technology, for example, operate at GHz frequencies under advanced signaling methods like orthogonal frequency-division multiplexing (OFDM) and fast frequency hopping to maximize link reliability and minimize interference with other services. Circuits that perform at high frequency with high switching speed are extremely sensitive to active and passive device models, distributed layout parasitics, substrate coupling effects, interstage impedances, IC packaging and power supply noise. Providing new methods that accurately characterize layout and other parasitic effects in RFIC design is more important than ever to first-pass success. Of critical importance is the design flow and modeling for custom integrated circuits that include RF circuits on the analog front-end, analog and mixed-signal circuits at baseband, and digital signal processing on the back-end.

This article details the development of an RF and analog design and verification method for complex systems that include custom RF and analog circuits. It combines the 0.13 µm RFCMOS process from UMC with a range of electronic design automation tools, such as the advanced circuit simulation and electromagnetic extraction tools from Ansoft and other established vendors. Ultrawideband (UWB) multiband orthogonal frequency-division multiplexed (MB-OFDM) radio circuits are used to demonstrate the process technology, EDA tools and design flow.

Many RFICs contain the analog-to-digital converter (ADC), digital-to-analog converter (DAC), phase-lock loop (PLL), and possibly a digital synthesizer. These functions are generally created in a mixed-signal environment and then integrated on-chip. Verification of these blocks is still performed using SPICE-level circuit simulators for critical accuracy. The addition of high-performance circuit simulation technology combined with a high-frequency simulation component and layout electromagnetic extraction, into the design flow creates opportunities for SoC designers to achieve first-pass silicon success.

• System design/behavioral modeling — Figure 1 is a functional chart of the typical RFIC flow and indicates the tools. The process begins with system design and behavioral modeling test bench development. Common modeling approaches for UWB circuits are to use Matlab, a high-level language like C, a hardware description language (HDL) like Verilog-A or VHDL-AMS, or dedicated system simulators like the one in Ansoft Designer. These tools are effective in creating a behavioral simulation of a system that may contain RF, analog and digital sections. Behavioral models for each of the blocks in a system (e.g., DSP and radio transmitter and receiver) can be created using the aforementioned tools. The level of detail in each behavioral model depends on the requirements of the analysis and the maturity of the project. By modeling the full chip within a top-level test bench, verification of critical system performance in terms of constellation plots and metrics such as error-vector magnitude (EVM) or bit-error rate (BER) can be performed. Circuit block specifications are developed to define such metrics as gain, return loss, noise figure, sensitivity, and effective number of bits (ENOB) for the data converters.

  This behavioral test bench serves as the framework for more complex mixed-level simulations, where blocks can be inserted at the transistor level and verified in a system context. It allows designers to make a trade off between analysis rigor and simulation speed by inserting critical blocks at the transistor level and well-characterized blocks at the behavioral level. Continuous verification of system performance as blocks mature can be performed to track system evolution during the design process. Problems can be detected and mitigated early in the design cycle allowing corrective measures to be performed. Block design by disparate design teams can occur concurrently and assembled into the top-level simulation as they become available.

  Circuit includes all baseband DSP and signal-conditioning circuits, radio circuits, and a multipath fading radio channel model. In this example, the behavioral modeling tool used for the UWB circuit is Ansoft Designer. A custom library of behavioral components for the UWB baseband signal processing including data scrambling, convolutional encoding, puncturing, symbol mapping and OFDM symbol generation, is provided by Ansoft and UMC. These models represent a Multiband OFDM Alliance (MBOA)-compliant system library.

• Circuit design — The next step is circuit design using idealized interconnect and foundry design kit device models. Circuits at this level are used for early design trades to select designs that meet performance specifications. Circuit simulation is performed in the time and frequency domains to characterize critical performance metrics. The choice of domain depends on the circuit, type of simulation and desired output. The Nexxim circuit simulator, fully integrated into the Cadence RFIC design flow, performs time-domain simulation with an optimized transient simulation engine. It performs frequency-domain simulation using a high-performance harmonic balance engine.

  The value of transient plus harmonic balance in a single simulator is made apparent by time and frequency domain simulations on RF circuits. Figure 2 is the schematic for the UWB receiver analog baseband including the baseband filter and variable gain amplifier for automatic gain control (AGC). Peripheral elements surrounding the core circuit represent the circuit test bench that provides in-phase (I) and quadrature (Q) inputs and outputs and various control and power supply voltages. This circuit is designed using the UMC 0.13 um foundry design kit (FDK) models. Simulations were performed using Ansoft's Nexxim circuit simulator. Figure 3 provides typical time-domain results for the circuit including the input waveform for a complex OFDM input and the output I and Q channel responses for a single UWB frame using transient simulation. A single process design kit and associated environment enables a smooth determination and selection of the simulation algorithm desired. Results are presented through a display appropriate for the selected simulation type. As circuits are completed at block level, they are verified within the top-level context with behavioral stimulus and descriptions for the surrounding chip.

  Note that to improve the fidelity of the simulation, on-chip passive elements like spiral inductors and metal-oxidemetal (MoM) capacitors can be synthesized, extracted and added to the circuit simulations. The passive models provided in a foundry design kit are highly accurate so long as design rules are followed and parameter ranges are not exceeded. For device topologies outside those provided in standard design kits, a mechanism such as UMC's electromagnetic design methodology (EMDM) can be used.

• Circuit layout — The next step in the process is to perform circuit layout. Automated design-rule-driven and connectivity-driven layout may be used judiciously, especially to take advantage of direct ties to schematic and design-rule checking (DRC). Critical analog blocks are generally manually routed using a full custom approach to ensure that highly sensitive analog circuitry meet specifications.

  As layouts are completed, electromagnetic simulation is used to provide highly accurate models for interaction of passive components and interconnect. For example, several spiral inductors may be selected as highly critical and a target for EM simulation in a single project. These EM simulation models can replace the models that were created earlier in the design process, and can be mixed and matched with the existing models. This gives the designer control over the passive modeling process, and enables the ability to trade off runtime vs. accuracy.

  An emerging capability for sensitive blocks like VCOs allows the extraction of the full layout at the block level using full-wave 3-D electromagnetic simulation. The performance of simulation tools and computer platforms continues to improve and it is possible to use 3-D simulation on critical radio blocks. This rigorous method simulates all high-frequency layout effects including on-chip inductors, interconnect, coupling between on-chip passives and to other interconnect structures, and substrate coupling. No assumptions are made regarding parasitics or coupling. Of course, the net-based RLC extractors have their place in the RFIC flow, but there is always designer input to manage which parasitic effects to include. It is not always clear which parasitic effects are most critical in the circuit context. Rigorous EM extraction of the entire block removes any doubt in the process.

• Parasitic extraction — The next critical step is to extract package parasitics and add those effects to the circuit simulations. At RF frequencies even the smallest amount of lead inductance can have a significant effect on circuit performance. The typical schematic for a UWB radio receiver includes the T/R switch, variable gain LNA, balun, I/Q demodulator and baseband filtering/AGC. This circuit was used to examine the effects of package parasitics on circuit performance. Figure 4 is a plot of the small signal performance of the circuit, with and without ground and supply lead inductance. Results show that the ground inductance, common to the first and second stages of the LNA, cause the circuit to oscillate. In the same simulation it was observed that the small signal gain of the LNA decreased by ~15 dB. Adjustments to the design of the various blocks were performed to stabilize the circuit.

• Full-chip verification — The final step prior to tape-out or additional chip integration is to perform full-chip verification in a system (behavioral) test bench. The verification can include transistor-level circuits for multiple circuit blocks with incorporation of all extracted parasitics. The system should allow designers to select the particular level of abstraction for individual circuit blocks in order to make reasonable trades between accuracy and simulation run time. For full-chip verification of radio transceiver transistor-level circuits within a system test bench, MBOA bit and frame accurate time-domain waveforms are automatically linked to the input of the receiver circuit. Circuit simulation is performed on the full receive chain with all extracted parasitics included.

The lifespan of wireless products is typically 12 to 18 months. Avoiding a program slip for re-spin can make the difference between successful design-in and missed opportunity. The RFIC design flow presented here for a UWB circuit provides a methodical approach to the design, simulation, and integration of complex SoCs. It is applicable to many diverse applications from sophisticated analog-digital SoCs containing wireless front-ends to simpler RFIC devices that only contain RF circuit blocks. By allowing continuous monitoring of project development using system-level verification and co-design with transistor-level circuits, fabless design organizations can establish true metrics for design feasibility and efficacy. The need for this flow increases as technologies scale to smaller technology nodes where parasitic and interconnect effects are more significant. The adoption of newer methods like the proposed RFIC design flow is no longer a question of if, but when.

Lawrence Williams is director of business development at Ansoft Corporation. He has more than 18 years of experience in electromagnetics and communications engineering and has published numerous technical papers on the subject. He received his Masters, Engineers, and Ph.D. degrees from UCLA in 1989, 1993 and 1995, respectively.

Albert Yen is mixed-mode and radio frequency technology manager at UMC. He received his BSEE from the Naval Academy, Taiwan in 1981, MSEE from the Naval Post-Grad School, Monterey, Calif. in 1989 and Ph.D. from the University of Florida in 1995.

RSS    Save to Del.icio.us  Digg This