High-speed serial ADC is JESD204 compliant
LTC2274’s
new high-speed two-wire serial interface greatly reduces the number of data input/output (I/O) lines
required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single,
self-clocking, differential pair communicating at 2.1 Gbps...
Understanding state of the art in ADCs
The article investigates key parameters that enable users to choose the right ADC based not only on performance, but cost and other tangible and intangible aspects of converters...
High-speed serial ADC is JESD204 compliant
LTC2274’s
new high-speed two-wire serial interface greatly reduces the number of data input/output (I/O) lines
required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single,
self-clocking, differential pair communicating at 2.1 Gbps...
Understanding state of the art in ADCs
The article investigates key parameters that enable users to choose the right ADC based not only on performance, but cost and other tangible and intangible aspects of converters...
Standardizing smart antenna API for SDR networks
In addition to defining the smart antenna application programming interface (API), this article will also describe the smart antenna API in detail and explore its benefits. Plus, it will introduce the smart antenna working group and the process they are following in developing this API, as well discuss steps toward standardization....