High-speed analog to digital converters (ADC) and large field-programmable gate arrays (FPGA) have allowed designers to design compact solutions that were unthinkable a few years ago. This article discusses how a 16-channel frequency modulation (FM) demodulator operating in the intermediate frequency (IF) region may be implemented in a single slot, and builds on two articles previously published in RF Design^[1,2]. The system implemented here is capable of digitally tuning to 16 separate FM bands, downconverting the signal to produce complex baseband outputs and performing a multichannel FM demodulation in a FPGA core.

This article describes an example implementation that can handle an FM bandwidth of 300 kHz. This supports an FM with 40 kHz message bandwidth and 105 kHz FM deviation. The implementation presented here easily handles a wide range of applications including sonobuoy and tactical communication applications. The 16-channel demodulator is implemented in a modular fashion as two eight-channel demodulator blocks. The eight-channel FM demodulator uses less than than 4700 slices, seven 18 × 18 multipliers and 16 18 kbit random access memory (RAM) blocks found in a Xilinx FPGA^[3].

Classic designs are being migrated to SDR-based implementation, and requirements for reconfigurability, space and size reduction are becoming crucial. SDR offers the most benefit in multichannel scenarios where high-speed signal-processing modules can process multiple channels without duplication of expensive processing modules. FPGAs are also playing a significant role for baseband processing and offer reconfigurability and space saving that is crucial for a variety of applications. This multichannel receiver can be used as, for example, a sonobuoy receiver, a tactical communication receiver or a next-generation wireless communication receiver. The FPGA-based implementation allows the user to reconfigure the same hardware into multiple profiles, resulting in significant space savings for multimode applications. Moreover, logistics support and spare parts inventory are greatly reduced.

The entire multichannel receiver can be delivered in a single-slot implementation with capacity to spare as shown in Figure 1. The single- slot receiver comprises two PMC modules: a high-speed ADC module with 16 digital downconverters (DDC) [ICS-554] and a FPGA-based PMC module [ICS-1580]. The ICS-554 allows the user to digitize up to four IF signals and digitally tune up to 16 frequency-division multiplexed (FDM) channels. The DDCs in the ICS-554 are programmed for a decimation factor of 64, which produces a complex output data rate of 1.5625 Msamples/s at a 100 MHz ADC sampling rate. Note that the data rate is four times higher than the Nyquist data rate of 390 ksamples/s (complex) for a 300 kHz RF bandwidth. These FDM channels (FM-modulated complex baseband signal) are then sent to the ICS-1580 module for FM demodulation (Figure 2). For ease of implementation, the 16-channel FM demodulator is implemented as two eight-channel demodulators.

The FM demodulation process can be characterized as:

m(t) = d(Φ)/dt, where phi is the phase of the received signal.

With a complex baseband representation (I, Q), Φ = atan(Q/I). Substituting this in the equation above and expanding out d(atan(Q/I)), the baseband message signal may be recovered as:

(I*dQ — QdI)/(I^2 + Q^2).

This is the heart of the FM demodulation function implemented in FPGA as shown in Figure 3. The automatic scaling function ensures that the output of the divider is a full-scale 16-bit number. This produces near full-scale baseband output for a wide range of RF signal power, in effect implementing a digital automatic gain control (AGC) functionality. The various settings are summarized in Table 1.

A detailed description of the hardware used and the various functional blocks programmed in the FPGA follows.

The ICS-554 and the ICS-1580 PMC modules that enable the build up of the system are described here.

• ICS-554

  A four-input high-speed ADC card capable of sampling at rates up to 105 MHz. Up to 16 onboard narrowband digital tuners enable users to implement a compact multichannel receiver solution. The maximum bandwidth per channel is 2.5 MHz for the 16 narrowband channels. Multiple channels may be combined to provide up to four channels at 10 MHz each. The onboard DDCs allow the user to digitally downconvert the signal and reduce the effective data rate for each channel. Digital tuning is achieved by writing a tuning word for the numerically controlled oscillator (NCO). Digital retuning is thus an extremely fast process and enables the receiver to serve as a very fast frequency-hopped system. More information regarding the ICS-554 is available from^[4].

• ICS-1580

  A PMC module with a Virtex-II Pro device (XC2VP70). The FPGA is directly connected to 64 Mbytes of synchronous dynamic random access memory (SDRAM) arranged as four independent banks and 16 Mbytes of QDR-II SRAM arranged as four independent banks. Four multi-Gigabit Tx/Rx links from the FPGA are available on the front panel and enable high-speed data movement in a multiboard scenario. This would allow multiple ICS-1580s to be interconnected to increase effective FPGA resources. The 64 user I/O lines of the PMC module are also connected to the FPGA and are used to transfer data from the ICS-554 to this module. More information regarding the ICS-554 is available from^[5].

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