This block is the heart of the FM demodulation process and is implementing the differentiation of the phase of the received signal. The DDCs produce a complex baseband (I,Q) representation of the received signal. The implementation of the (I*dQ — QdI)/(I^2 + Q^2) is carried out in two steps. In the first step, the numerator (I*dQ — QdI) and the denominator (I^2 + Q^2) are first computed. The differentiation function is approximated by the difference operator. Thus:

dI = I(n) — I(n-1) & dQ = Q(n) — Q(n-1). After algebraic manipulation the numerator becomes:

I(n-1) * Q(n) — I(n) * Q (n-1).

The denominator is calculated in a straightforward fashion. The multipliers are implemented using the 18 × 18 hardware multipliers available in the Xilinx FPGA. The division is performed using a Xilinx LogiCORE divider block. The availability of dividers that can be easily and economically implemented in a FPGA has made possible implementation of a much wider variety of DSP algorithms in FPGA. A fixed point divider is implemented in this example.

The design targets a system with approximately 300 kHz RF bandwidth with about 40 kHz baseband signal bandwidth. Thus, an FM system with 105 kHz frequency deviation and 40 kHz message bandwidth will be easily accommodated as the bandwidth of such a system is about 290 kHz (= 2*(105+40)). The Nyquist data rate for carrying this bandwidth is about 390 ksamples/s (complex), which translates to a DDC decimation of 256 at a 100 MHz sampling rate. However, at this reduced sampling rate, the approximation of the differentiation reduces the distortion performance. To alleviate the problem, a 4x oversampling ratio has been selected as compared with the Nyquist rate.

The output of the phase discriminator is the baseband message signal (40 kHz bandwidth in this example). However, the output data rate is about 1.56 MHz, which is much more than required. Having a very high data rate causes an undue burden on the host system, which has to transfer and process the data. To reduce the data rate, a decimating multiply-accumulate (MAC) low-pass finite impulse response (FIR) filter is used. The decimation factor for the FIR is chosen to be 16, which produces a baseband data rate of 97.65 kHz, sufficient to handle the message bandwidth of 40 kHz. The low-pass FIR has a passband of 42 kHz and a stopband of 48 kHz. As the input data rate (1.56 Msamples/s per channel) is significantly lower than the 100 MHz clock used in the FPGA fabric, multichannel operation is possible without consuming additional FPGA resources.

FM systems are typically narrowband applications. This allows multichannel implementation in relatively small FPGAs. FPGAs typically run at very high speed. In the example shown here, the FPGA was a Xilinx Virtex II Pro device (XCV2P70) running at 100 MHz. The relative occupancy is shown in Table 2.

The compact design is achieved by running the FPGA at a much higher frequency than the input data rate. Thus, the same resources (multipliers, slices, etc.) may be used to process multiple channels. This allows the developer to implement additional functionality in the design. Other FPGAs are now available that run at faster clock rates enabling more functionality to be packed in the same device.

The approximation dQ = Q(n) — Q(n-1) causes non-linear distortion. A simple way has been used to reduce the distortion by oversampling as described earlier. The higher complex baseband output data rate from the DDCs allows greater granularity in the differentiation, reducing the distortion. Software-based floating-point implementation has shown that 4x oversampling (as compared with the Nyquist rate) reduces the harmonic distortions by about 30 dB (compared to the case when the outputs are at the Nyquist rate). Additional improvements may be obtained with a higher oversampling factor.

The test setup used to characterize the multichannel receiver is shown in Figure 4. The FM demod data is collected and a FFT (using a flat-top window) is used to analyze the performance. Figure 5 and Figure 6 show the performance at two input levels: -10 dB and -20 dB below the full scale of the ADC input. The ADC full-scale value is about 5 dBm. It can be seen from the plots that the demodulated output signal level is preserved. The estimated SINAD for the -10 dBFS input case (Figure 5) is 28.0 dB, while that for the -20 dBFS input case is 23.2 dB.

This article describes a single-slot multichannel receiver that is ideal for multimode SDR-based reconfigurable solutions. As an example, a multichannel FM demodulator core has been implemented with extremely low FPGA resource utilization demonstrating the power of today's high-speed FPGA devices in communications systems.

1. RF Design, May 2004, “FPGA-based Application for Software Radio,” Angsuman Rudra.

2. RF Design, July 2003, “Multichannel Multiband VHF Software Radio-based Receiver Eliminates RF Downconversion,” Angsuman Rudra.

3. Xilinx Virtex-II Pro Data Sheet (www.xilinx.com).

4. Tech Note No. 45: “ICS-554 4-Channel, 105 MHz ADC PMC Module with DDCs, Xilinx FPGA and PCI 64/66 Interface” (http://www.ics-ltd.com/TechNotes.cfm).

5. Tech Note No. 54: “The ICS-1580 FPGA DSP Board with High-Speed Inputs in PMC Format,” (http://www.ics-ltd.com/TechNotes.cfm).

Angsuman Rudra obtained a B. Tech degree from IIT Kharagpur in India in 1992, a Masters degree in Electronics and Electrical Communications Engineering from Carleton University in 1996, and an MBA from the University of Ottawa in 2001. Previously with Nortel, he joined ICS Sensor Processing in 2001, where he is currently director, systems. He is a Professional Engineer in the state of Ontario and a member of IEEE.

Alexis Bose holds a BASc in Systems Design Engineering from the University of Waterloo. He has five years of experience in software and hardware systems related to communications, biomedical and defense. He joined ICS Sensor Processing in 2003 as an FPGA systems engineer, and has worked on numerous software-defined radio and radar projects.

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