The popularity of reconfigurable radios is increasing as wireless infrastructure equipment manufacturers try to design platforms that cover multiple frequencies and air interfaces. The market continues to strive to achieve the ideal of a software-defined radio (SDR). While this research continues, incremental developments are taking place that provide common platform designs. Designs are then configured during manufacture, providing an overall savings in development costs.

Because of their simplicity and the limited number of spurious components they generate, direct-conversion signal chains are becoming a popular architectural choice in many radios, especially in reconfigurable platforms. IQ modulators and demodulators are key components in direct-conversion transmitters and receivers. This article will focus on using IQ modulators in reconfigurable radio transmitters.

Like many evolving technologies, the term reconfigurable radio defies a broadly agreed definition. A reconfigurable radio might be defined as one or more of the following:

1. A common PCB that can be selectively populated during manufacture to provide operation at a particular frequency using one of a number of possible air interfaces.

2. Fixed hardware that can operate at one frequency using one or more air interfaces.

3. Fixed hardware that can operate at multiple frequencies using one air interface.

4. Fixed hardware that can operate at multiple frequencies using multiple air interfaces.

Most systems engineers would agree that the last point above describes a true SDR. Figure 1 shows a conceptualization of a direct-conversion signal chain. First, the challenges associated with designing such a signal chain will be considered, and then upconverter architecture implementations will be examined.

The data to be transmitted is first encoded in a digital baseband processor. In a reconfigurable radio, this processor will require a certain level of flexibility so that it can be reprogrammed as the air interface changes. While this function could be implemented using a standard digital signal processor (DSP) or using a field-programmable gate array (FPGA), the main challenge is to put in place enough processing power so that the system is capable of encoding the most complex of the air interfaces to be supported. The downside of this approach is that when the processor is encoding a low data rate signal into a relatively simple air interface (e.g., QPSK), processing power will exceed demand.

Once the data has been encoded and filtered in the digital domain, it is converted to an analog signal that can be in complex (I, Q) or real format (low IF). In either case, this signal must be filtered to remove Nyquist sampling images and broadband noise. This presents the first hardware challenge to implementing a complete software radio since different air interfaces will require different filter bandwidths and shapes. As a result, some kind of programmable filtering will be necessary. There is, however, an alternative to this. If a DAC is selected with high resolution and a very high sampling rate, its broadband noise will be low and Nyquist images will appear at high frequencies. As a result, it may be adequate to implement a fixed baseband filter whose corner frequency is higher than the broadest bandwidth to be transmitted but still low enough to remove the Nyquist images. As in the case of the baseband processor, the downside of this approach is that high-performance hardware (i.e., the DAC's LSBs) will sometimes go unused.

The next step is to upconvert the baseband signal to the radio frequency. In general, one or more local oscillators are required to mix the RF signal with the baseband signal. Although it is not difficult to design a frequency-agile oscillator, which can operate within a particular frequency band, design of broadband oscillators is more challenging. Generally, the design is limited by the tuning range of the voltage-controlled oscillator (VCO). Since VCO tuning ranges are typically 100 MHz to 200 MHz (for VCOs operating in the 1 GHz to 3 GHz range), an alternative approach must be taken if the radio is to operate across a multiGigahertz range. One option is to operate the PLL/VCO at a high base frequency and use programmable frequency dividers to set the frequency at the input of the upconverter.

In addition to this requirement, the phase noise requirements and phase lock time of the oscillator will change with the air inter-face. Once again this calls for design of an oscillator whose phase noise and lock time conform to the requirements of the most demanding air interface.

Inside the upconverter, reconfigurability creates additional challenges. If a superheterodyne upconverter is chosen, careful frequency planning will be required if broadband frequency agility is required. In addition, the filters that are required at each intermediate frequency (IF) will have to have programmable bandwidth to deal with the variable bandwidth of the signal being transmitted.

Regardless of the architecture of the upconverter, a number of unwanted components will appear at its output; the architecture will merely influence the location and number of these unwanted components. There will always be some broadband noise that may or may not require filtering.

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