A true software-defined radio (SDR) front-end IC presented by IMEC earlier this year at ISSCC 2007 incorporates an SAR ADC design with record-breaking performance. Specifically, the 0.7 mW, 50 Msps ADC presented by IMEC achieves a record-breaking figure of merit of 65 fJ per conversion step. While targeting SDR applications, the ADC design is also suited for nomadic applications in the IT realm.

This front-end chip is widely programmable for all present and future standards between 174 MHz and 6 GHz. Its low power consumption is of great importance for next-generation handheld and battery-powered devices, and the IMEC SAR ADC is also well suited for future SDR applications facing the same battery-life challenges.

Specifically, its power scales linearly with the clock rate over a very wide range. Furthermore, it is implemented in pure digital CMOS technology, making it very well suited for scaling to the 45 nm CMOS node and below. The design is also available as 'white box IP' for transfer to the industry.

Instead of the active charge redistribution in the capacitor arrays of a conventional successive-approximation (SAR) architecture, the low-power architecture of the IMEC SAR ADC uses a passive charge-sharing concept to sample the input signal and to perform the successive-approximation cycling. As a consequence, the SAR operation is no longer based on voltage comparisons. It operates completely in the charge domain, which yields the performance of the design. This way, the fundamental power limits of the original SAR architecture are overcome.

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