Pentek Inc. has unwrapped a high-performance, high-resolution software radio module 7151. It’s four 200 MHz 16-bit analog-to-digital converters (ADCs) feed a proprietary FPGA IP core that delivers 256 channels of digital down conversion (DDC). Designed for GSM cell-phone monitoring and signal-intelligence applications, the model 7151 leads the industry with the best resolution and highest channel density in the market today, stated Pentek.

With independent frequency tuning for each of the 256 DDC channels, the model 7151 can down-convert any signal within any of the four digitized 100 MHz input bands, significantly enhancing the efficiency and diversity of signal-intelligence applications. Arranged in four banks of 64 DDC channels, each bank can be configured for a unique output signal bandwidth to accommodate applications requiring mixed signal types or multiple modulation schemes. Each DDC bank can be independently sourced from any one of the four ADC converters, which are typically assigned to specific antennas. As a result, the software module provides extreme flexibility for simultaneously capturing hundreds of signals spanning a wide range of modulation types, signal bandwidths and antenna sources, Pentek said.

The model 7151 is fully supported with drivers and it comes ready to use with the FPGA code already developed and installed. The front end accepts four +10 dBm, full-scale analog RF or IF inputs on front-panel SMC connectors into 50 Ohms, with transformer couplings to four 200 MHz, 16-bit ADCs. The digitized outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal-processing operations. The 200 MHz ADCs accommodate input signal bandwidths of up to 100 MHz, representing a 37% increase over previous Pentek modules.

All of the 64 channels within a bank share a common decimation setting that can range from 128 to 1024, programmable in steps of 64. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 156 kHz to 1.25 MHz. Plus, each 64-channel bank can have its own unique decimation setting supporting as many as four different output bandwidths on the board. This flexibility allows customers map the DDC to their own particular application.

The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0.8*ƒs/N, where N is the decimation setting. The rejection of adjacent-band components within the 80% output bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I and 24-bit Q samples at a rate of ƒs/N.

Any number of channels can be enabled with each bank, selectable from 0 to 64. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank. Additionally, four output MUXs can be independently switched to deliver either ADC data or DDC data into each of the four output FIFOs. This allows users to view either the wideband ADC data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.

The 7151 PMC module can be attached to any PMC carrier board. Furthermore, a 4207 processor board with its two mezzanine sites can support two 7151 PMCs delivering 512 DDC channels in a single VME slot, noted the supplier. Software and software-support packages are available for Linux, Windows and VxWorks operating systems. The model 7151 PMC module is available for $14,500. Delivery is 10 to 12 weeks ARO, according to Pentek.

www.pentek.com

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