The baseband module features a Xilinx Virtex-4 SX35 FPGA and a TI TMS320DM6446 DSP chip. The TI chip contains a TMS320CC64x+ digital signal processor (DSP) core and an ARM9 general-purpose processor (GPP) core. Furthermore, the SDR development platform includes a unique power measurement API. This API measures the loading of the FPGA, DSP and ARM, and reports real-time power data. This allows developers to extract important information such as burst and peak power for a specific data rate, enabling them to accurately estimate battery life. It also enables developers to assess the power impact of various system configurations. For example, the developer can experiment with different system partitioning between the FPGA and DSP to obtain an optimal power/performance balance.

Likewise, the digital-processing module capitalizes on the performance and architecture benefits of TMS320DM6446 system-on-a-chip (SoC). The high-performance DSP core streamlines complex signal processing, while the GPP supports network and application processing. Plus, the DM6446 SoC comes complete with a full set of peripherals necessary for SDR, including serial ports, USB and Ethernet connections and DDR2 and NAND flash memory.

The data-conversion module includes two ADS5500 ADCs, offering 14-bit performance at 125 Msps, and one DAC5687, a 16-bit dual-channel DAC with 500 Msps. The standard RF module included in the kit covers from 360 MHz to 960 MHz with a selectable 5 MHz or 20 MHz bandwidth, supporting a wide range of applications. The platform also uses TI's MSP430 ultralow-power MCU and power management technology.

Because cost and power consumption are two critical factors when designing for portable applications, developers need to have easy access to actual power consumption and processor utilization. While measuring average power gives a broad idea of the global consumption, it does not provide any information on pieces of a waveform that are active only part of the time. For instance, measuring a radio that runs a TDMA waveform will only provide an average consumption of the transmit, receive and idle (or other) modes. For this purpose, the platform provides to the developer embedded power-monitoring capability separately for the SoC DSP and FPGA processors. This way, it is possible to associate power measurements with specific portions of the waveform. Processor utilization is valuable information for developing end products. First, it provides the knowledge required to scale down to a smaller, cheaper, less power-consuming processor, and second, to select the minimum clock frequency needed that also impacts power consumption. Additionally, it helps in deciding how a waveform should be partitioned, or repartitioned, amongst the processing choices on the system. Moreover, power measurements can be brought in the model-based environment, allowing it to profile and display power consumption versus time and processing activity.

Also, it is important to know that between the two main design approaches (C/VHDL versus model-based design) lie multiple options that developers can take advantage of. As a first example, part of a team might prefer to hand-code DSP algorithms while the other part of the team would like to take advantage of model-based design and code generation for the FPGA. The board's development package supports such situations. Model-based design also supports IP reuse by being able to include legacy code among the other blocks. In the Simulink environment, this is done by using S-functions for the DSP, and black boxes for the FPGA. On the other hand, a developer can integrate his or her model-based algorithms to the low-level coded design of the rest of the team with the use of Embedded Coder, another tool from The Mathworks tailored for embedded processors. In the following sections, we will take a closer look at a simple modulation designed entirely with a model-based approach, and briefly describe a more complex design (a GSM modulation) done using a mixed design flow (model-based design for the FPGA, and C/assembly for the SoC DSP).

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