As already established, noise level is directly proportional to input bandwidth (SNR is inversely proportional to bandwidth). As seen in equation 2, noise is proportional to Boltzmann's constant and absolute temperature and inversely proportional to the sample capacitor.

As stated earlier, noise density decreases with sample rate. As both SNR and sample rate improve, the thermal noise floor continues to reduce. While a long way from device thermal noise, current wideband converters are approaching the noise level of an optimally matched antenna (-174 dBm/Hz) making them easier to use in systems with even modest conversion gain. Current technology is within 20 dB of reaching this threshold and new techniques are being discovered for reducing the noise level through signal processing and better analog design. Figure 3 depicts recent SNR trends in high-speed Nyquist converters, while Figure 4 shows a similar trend for NSD.

In most applications, this level of performance is only achieved when using a low jitter clock source^[6,7]. In recent years, low jitter oscillations, PLLs, DDS and other devices^[8] have become available that can both clean up reference clocks and provide high fan outs to multiple devices in a system. Current ADC technology provides clock jitter as low as about 50 fs creating quite a challenge to system clock designers. Only when system designers provide clock jitter this low can full performance be expected from ADCs, especially when operated at high IFs.

Better spurious performance is achieved by wider bandwidth. A system with a large input bandwidth is less prone to slew rate limitations, allowing the ADC to better track the signal input to the device. As seen in equation 3, bandwidth is proportional to 1/C and since a fast slew rate translates to spurious performance, the same 1/C relationship applies.

Therefore, for optimal spurious performance a wide input bandwidth is desirable. This means the sample capacitance must be as small as possible. However, from equation 2 we know that making the sample capacitance small, the increased input bandwidth allows more noise to enter the front end of the ADC and be spread across the Nyquist spectrum. Thus, SNR and SFDR must always be traded off between one another. Academic literature has continually produced work that explores the key to significantly improved performance. The studies examine how to improve the sampling switch mechanism while optimizing a reduced sample resistance and smaller capacitor^[9]. Figure 5 reflects the performance improvements in SFDR over the years.

Given the trends for both SNR and SFDR, how do they stand up against system requirements? Table 2 shows required performance by air interface for popular wireless standards. These specifications are for wideband multicarrier performance without the benefit of automatic gain control, similar to what would be required for a software-defined receiver capable of processing that standard. As seen, GSM/EDGE in the 900 MHz band is the most challenging and currently not possible with existing converters (current systems use single-carrier design with narrowband filters and AGC). Referencing Figure 3 and Figure 5 clearly shows that for the remaining standards, multicarrier SFDR is entirely possible from an ADC perspective.

Unlike digital designs where Moore's Law^[10] is cited, analog and mixed-signal designs cannot constantly be shrunk to take advantage of smaller geometry processes. There are at least two fundamental process limitations. Unlike digital designs, analog blocks are not designed in verilog but instead optimized at the transistor level for the specific process to optimize power, noise, and linearity. When moved to a new process, the optimization must be completely redone. In fact, many times, totally new design topologies are required, forcing new designs and architectures. In addition, some processes are simply not compatible with analog signal processing and variations must be made.

Design reuse is similarly limited to product variants or derivatives on the same process. It is not possible to take one 0.35 µm-based design and migrate it to 0.18 µm and expect performance to be the same or better. In general, it takes a few product generations for designers to understand the performance curves of a new process and advance the performance curves for high-speed ADCs. As stated, using the larger transistors on the finer line process will waste expensive die space and probably will no longer be optimized. Designing product derivatives or close variants are highly possible within the same process. In fact, this is often seen in products where single, dual, quad and octal channels are required. Likewise, reuse is seen in cases where integration with additional analog and digital features is required. At the design core level (fully functional ADCs) products like ADI's AD9228 12-bit 65 MSPS quad ADC are easy to reuse across a large portfolio of standard products including octals and more application-specific products that could include gain, filtering and mixing analog functions. At the circuit level, functions such as output drivers, references and amplifiers are easily reused as long as the processes remain the same.

Likewise, mixed-signal ICs never follow the same cost reduction as experienced with digital chips. Once a product is released, its design is fixed and forever tied to that process geometry. A common method to reduce the cost (and price) is to improve product yield and increase volume or to design an ADC on a new, lower-cost process. Unfortunately, this results in a reduction in performance over previous generations. While this does correct in future generations, jumping processes frequently results in reduced performance from one device to the next.

When devices are migrated to new processes, it is often the desire to make the new device pin and function compatible. Unfortunately, it may behave differently in a number of ways. Not only will dynamic performance be different as outlined above, but analog inputs (range and impedance) and digital output characteristics may be different. More important, newer processes typically have smaller breakdown voltages and, therefore, support lower supplies. While most processes do have the ability to retain supplies of their previous generation, maintaining supplies from two or more generations is becoming increasingly difficult as geometries continue to reduce. These issues make it almost impossible for pin-compatible drop-in replacement for the older device without changes to supplies, input matching networks and receiving logic gates.

With the introduction of 0.35 µm CMOS converters, the inclusion of digital features to the core ADC offer many interesting functions beyond the standard output data format. New feature sets include shuffling, dithering, output test patterns, built-in self test and a plethora of other user features^[12]. However, accessing these features can be problematic. Many new high-speed converters now offer SPI interfacing to access the rich features sets once reserved for slow-conversion ADCs. Because these features are digital, they can now be easily transported from one design to the next, even across process changes because of their generation in Verilog or other digital language. Over time, many of these new features will emerge as ‘standard’ features of high-performance ADCs and will exist for many generations, even through process shrinks and changes.

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