A number of limitations exist in data converters. As mentioned, there is a natural conflict between SNR and SFDR. These conflicts are improved by advances in architecture and optimizations in process. While improvements have continually occurred over time, the process is at least partially reset each time a new semiconductor process is employed. Because of this, improvements often tend to be two steps forward and one step backward. Cost pressures push decisions to switch to newer processes whereas remaining on older processes would indicate that generational improvements in performance are possible but not necessarily a cost reduction.

Additional issues exist with moving to smaller geometries. As the geometry sizes decrease, breakdown voltages are reduced making it harder to design for performance. In terms of SNR where thermal noise may be considered ‘finite’ for a process or architecture, larger input swings can improve performance. If breakdown voltages constrain signal swing, SNR limitations may result. While this is not a problem for low-resolution converters, it is a big limitation for high-resolution converters, especially those with large input bandwidths. Similarly, lower breakdown devices offer only reduced overhead between analog signal swings and power supplies, implying poorer linearity from those devices. In summary, smaller geometries with lower breakdown values offer poorer noise and linearity performance.

Interfacing to the analog input is becoming more difficult. For low-frequency applications, this is not a big issue but as IF frequencies increase and direct RF sampling becomes a possibility, proper impedance matching to the source becomes more critical. At high frequencies, optimal ADC performance is only achieved when a proper match exists not only because the input is presented with a maximum of signal level but because ADC input behavior in terms of both noise and especially spurious is optimized^[5].

Clearly, SNR is on an improving trend. Based on noise spectral density, performance over the last 20 years indicates a solid 1 dBm/Hz per year. As for spurious, this report has provided antidotal evidence showing that SFDR performance has been constant for the last five to 10 years in the baseband region. While there is a clear need for full-scale performance in the range of -110 to-120 dBFS, consistent performance of only -95 to -100 dBFS is available in the base-bandregion today. At the same time, great attention has been paid to increasing SFDR performance in the mid and high IF regions with a result that usable IF frequencies as high as 450 MHz are not uncommon for some applications.

In addition to improvements in the analog signal path, improvements in the digital domain can also improve performance. With digital features such as shuffling, dithering^[13] and calibration becoming standard features on high-speed converters, it is clear that the ‘D’ is getting bigger in ADC. Each of these digital techniques has the ability to improve the linearity and noise performance of the converter under a variety of conditions.

In addition to improvements in process and Nyquist converters as described here, advances in other classes of converters holds potential and may displace these converters in some applications. As mentioned, another key to improved performance is improved clock sources. To achieve rated SNR, especially at high input frequencies, clock jitter must be minimized.

In the end, it is not just the ADC designer who is challenged to design a better ADC; the system designer is challenged to blend all of these aspects together. One must choose the right ADC based not only on performance, but cost and other tangible and intangible aspects of converters.

1. “Multicarrier CDMA2000 Feasibility,” Analog Devices Applications Note AN-808, Brannon and Schofield, www.analog.com.

2. “Multicarrier WCDMA Feasibility,” Analog Devices Applications Note AN-807, Brannon and Schofield, www.analog.com.

3. R.H. Walden, “Analog-to-Digital Converters Survey and Analysis,” IEEE Journal on Selected Areas in Communications. vol. 17, no. 4, pp. 539-550, April 1999.

4. B. Le, T.W. Rondeau, J.H. Reed, C.W. Bostian, “Analog-To-Digital Converters — Past, Present and Future,” IEEE Transactions on Signal Processing, vol. 53, no. 11, pp. tbd, November 2005.

5. “A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs,” Analog Devices Applications Note AN-827, Newman and Reeder, www.analog.com.

6. “Aperture Uncertainty and ADC System Performance,” Analog Devices Applications Note AN-501, Brannon, www.analog.com.

7. “Sampled Systems and the Effects of Clock Phase Noise and Jitter,” Analog Devices Applications Note AN-756, Brannon, www.analog.com.

8. AD9510 Datasheet, Analog Devices, www.analog.com.

9. M. A, Ali et al., “A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp.1846-1855, August 2006.

10. www.intel.com/museum/archive/history_docs/mooreslaw.htm.

11. “Pin-Compatible High Speed ADCs Simplify Design Tasks,” Analog Devices Applications Note AN-803, Clarke, www.analog.com.

12. “Interfacing to High Speed ADCs via. SPI,” Analog Devices, www.analog.com.

13. “Overcoming Converter Non-Linearities with Dither,” Analog Devices Applications Note AN-410, Brannon, www.analog.com.

Brad Brannon is a systems applications engineer for the high-speed converters group of Analog Devices. He has been with ADI since 1984 and specializes in analog-to-digital converters and wireless systems. He graduated from NC State with a BS in electrical engineering in 1983.

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