This approach involves managing trade offs. It requires the designer to understand how the device will be used and its resulting power needs, and to maximize power savings using as few discrete components as possible. An effective design may be able to capture the majority of the power savings capable within the device. Consider, however, that even an extra 5% or 10% of power savings could potentially result in several additional hours of battery life.

Another approach would be to separate as many of the power domains as possible, serving them with their own smart controller and related discrete voltage regulators to ensure that each function gets only the power it needs and can be controlled independently. While this approach will maximize power savings, it fails in several other ways.

First, it's highly complicated. Each set of discrete components adds a layer of complexity. It takes a tremendous amount of engineering time to choose all the components needed, and to develop the best process for connecting them. Also, as the number of components grows, so, too, does the number of potential problems. The testing process is greatly extended. With numerous controllers managing the needs of the device, it takes more time to track down and trace problems.

Second, it is expensive as each discrete part has an absolute cost.

Finally, it's highly inefficient. While this approach can reap more power savings than a design that uses far fewer discrete components, these additional components take up excessive room within the device. In other words, instead of wasting power, we waste space.

The delicate balancing act of minimizing a device's power needs with as few discrete components as possible is made even more challenging with today's much more efficient processors. Processors like the Intel Monahans, for example, may have 20 power domains. This applications processor gives us unprecedented abilities to conserve power, but how can we take advantage of that functionality most efficiently?

Modern processors require a modern power management solution, and an integrated SoC (Figure 1) allows us to maximize power savings while minimizing the space used inside the device. While the integrated chip is larger than any one of the voltage regulators, it is smaller than all of the components it replaces. It is a result of the economies of scale.

With an integrated solution, the voltage regulator components are combined at the silicon level. That reduces the need for packaging, resulting in one chip that is denser than the multiple chips it replaces. Additionally, the integrated component can share some functionality that would otherwise be duplicated between the individual voltage regulators, resulting in further space savings.

By significantly reducing the size of each of the individual voltage regulators, more regulators can be included in the device. This allows us to specifically tune each regulator to perfectly match the needs of the component it powers. This ability to highly optimize each regulator further improves power efficiency within the end product.

With a greater number of voltage regulators, we also gain more control over the power sent to individual components at run-time. If a particular feature is not in use, it is possible to reduce or cut power to it.

The ability to manage power needs at such an intimate level is not unique to an integrated solution. However, simply adding more voltage regulators and related discrete components would result in a device that is too large and too expensive to effectively compete in the marketplace. It is the size and efficiency of the integrated approach that makes this high level of optimization possible. Additional space savings can be attained by bundling other components, such as the audio subsystem and battery charger, on the same integrated chip.

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