With the methodology outlined above it is possible to compute ζ_e over a range of φ values for a specified threshold level. This provides a means to build a plot of ζ_e vs. φ that can serve as a tool for identifying the effective damping factor associated with a particular phase margin value (based on a specific threshold level). Since the above procedure yields t_THRESH and f_{c_min}, then it is a simple matter to also generate plots for t_THRESH vs. φ and f_{c_min} vs. φ.

Figure 6 through Figure 8 are plots that were generated using MATLAB to execute the procedure outlined above. The dashed trace indicates the raw data generated by the procedure. The solid trace is data after smoothing. The ripple that appears in the raw data can be attributed to the approximation of the slope of the envelope (the arrowed lines in Figure 4) rather than the true slope (the dashed lines in Figure 4). The results agree reasonably well with those presented in reference 1. The slight deviation in the values shown in the plots here with respect to those shown in reference 1 can be attributed to the same slope approximation error mentioned above.

The plots here were generated with the following parameters:

φ_min = 15°

φ_max = 80°

Δφ = 0.5°

N_THRESH = -10 nepers

t_LOCK = 100µs

The results given in reference 1 demonstrate that an “effective” damping factor (ζ_e) can be determined for a third-order PLL that is somewhat analogous to the commonly used damping factor parameter (ζ) in second-order PLLs. In reference 1, circuit simulations were used to generate the data for the time domain transient waveforms required to determine ζ_e. For a given phase margin (φ), multiple simulations were executed with various combinations of the transient step size and closed-loop bandwidth (ω_c) and the results averaged to arrive at a mean value of ζ_e for the specified φ. The technique described builds on the work given in reference 1 by eliminating the need to run multiple circuit simulations. Instead, the time domain waveforms are generated from the closed-loop transfer function after determining the necessary coefficients as described in references 2 and 3. This technique allows the analysis to be normalized to the closed-loop bandwidth and the transient frequency step size, which eliminates the need for multiple simulations and averaging. The caveat is the introduction of the small error associated with approximating the slope of the logarithmic error envelope rather than using the actual slope. However, the relatively small error introduced by this approximation is worth the dramatic reduction in processing time compared to the methodology used in reference 1. In fact, the procedure outlined above that produced Figure 6 through Figure 8 was executed in less than 10 seconds using a PC with a 2.4 GHz dual-core processor.

Click here for the enhanced PDF version of this article

1. Vaucher, C. S., “An Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time,” IEEE Journal of Solid-State Circuits, vol. 35, No. 4, April 2000.

2. Hawkins, D. W., “Digital Phase-Locked Loop (PLL)-Based Frequency Synthesizers: Theory and Analysis,” June 18, 1999, World Wide Web.

3. Keese, W. O., “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge Pump Phase-Locked Loops,” National Semiconductor Application Note 1001, May 1996.

4. Wolaver, D. H., Phase-Locked Loop Circuit Design, Prentice Hall, 1991.

Ken Gentile is a system design engineer for the Clock and Signal Synthesis Products Group at Analog Devices, Greensboro, NC. His specialties are the application of digital signal-processing techniques in communications systems and analog filter design. He holds a B.S.E.E. degree from North Carolina State University.

Previous 1 2 3